High quality epitaxial growth of heterostructures with large lattice mismatched materials is desirable for next generation electrical/optoelectronic devices and multi-functional integrated circuits. Conventional attempts to grow heterostructures such as GaAs on Si with misfit f of about 4.2%, involve methods of using: low-high two step growth, with thermal cycling; post growth annealing; strained superlattice buffers; and growth on 2°-off Si(001) and patterned substrates.
Nano-patterned growth (NPG), supported by the Luryi-Suhir model [see Appl. Phys. Lett. 49, 140 (1986)] has been suggested as a potential solution to lattice-mismatched heteroepitaxy. As a result, conventional NPG uses interferometric lithography and dry etching, by which In0.06Ga0.94As/GaAs heteroepitaxy (f˜0.4%) has been formed with a pattern period of 335 nm. While there is some controversy about the validity of the model, theoretical calculations suggest that increased misfit in the NPG requires pattern structures smaller than ˜100 nm for strain relief without formation of misfit dislocations. However, this scale is beyond the reach of many of large-area lithography techniques.
There remains a need for materials and methods for forming devices over large areas with lattice mismatched materials that are strain-relieved, and have low numbers of defects. Further, while some of currently available lithography techniques such as immersion interferometric lithography may provide a desirable small scale, a need remains for alternative methods to eliminate conventional lithographic processes along with the associated etching and hydrocarbon cleaning steps to simplify the manufacturing process and to reduce the manufacture cost.